1. Field of the Invention
The present invention relates to a memory device, and more particularly to a hybrid memory device.
2. Background of the Related Art
While static random access memory (e.g., SRAM) and read-only memory (e.g, ROM) generally operate as separate memory devices, a hybrid memory device contains both SRAM and ROM cells operating as a single memory device. Hybrid memory devices contain SRAM nodes coupled to ROM nodes. Therefore, data can be loaded directly from the ROM cell to the SRAM cell without passing through any external circuits.
FIG. 1 shows a related art hybrid memory device containing an SRAM cell 1 and a ROM cell 2. Both of those cells 1, 2 use two bit lines BIT, BIT'. The SRAM cell 1 uses a word line WL for selecting the bitlines BIT, BIT', while the ROM cell 2 uses ROM cell enabling signal RE for reading the ROM cell 2. Two nodes A, B in the SRAM cell 1 store data. The NMOS transfer (or access) transistors NA1, NA2 transmit data between the nodes A, B and the bitlines BIT, BIT', respectively, based on the word line signal on the word line WL.
The SRAM cell 1 includes a first PMOS transistor NP1 and a first NMOS transistor ND1 connected in series to form a first inverter. Similarly, a second PMOS transistor NP2 and a second NMOS transistor ND2 are connected in series to form a second inverter. A first node A is between the drain of the first PMOS transistor NP1 and the source of the first NMOS transistor ND1, while a second node B is between the drain of the second PMOS transistor NP2 and the second NMOS transistor ND2. The gates of the second inverter are connected to the first node A, while the gates of the first inverter are connected to the second node B. The NMOS transfer transistors NA1, NA2 transmit data between the first and second nodes A, B and the bitlines BIT, BIT' based on the word line signal on the word line WL.
The ROM cell 2 includes a first and second NMOS transistor NE1, NE2. The transistors NE1, NE2 are connected with the first and second nodes A, B of the SRAM cell through a first and second fuse F0, F1, respectively.
The SRAM cell 1 reads data directly from the ROM cell 2 as shown in FIGS. 2A through 2D at time t3. The SRAM cell 1 stores initial data in the nodes A, B when the ROM cell enabling signal RE is transited to a `low` level. That initial data is formed in the ROM cell 2 by masking. When the first NMOS transistor NE1 is connected with the first fuse F0, that first NMOS transistor NE1 is masked. The second NMOS transistor NE2 is in a normal state when the second fuse F1 is opened. In the SRAM cell 1 at that time, the first node A stores data at a `low` level and the second node B stores data at a `high` level according to a latch system of the SRAM cell 1.
When the state of the first fuse F0 is open and the state of the second fuse F1 is connected, the first node A stores data at a `high` level and the second node B stores data at a `low` level. Thus, the ROM data can be directly loaded to the SRAM cell 1 without passing through an external circuit because the nodes A, B of the SRAM cell 1 are connected to the ROM cell 2.
Once the data of the ROM cell 2 is loaded to the SRAM cell 1, the ROM cell selecting signal RE transits to a `high` level. Then, the word line WL can select the bitlines BIT, BIT' to perform a read/write operation at the SRAM cell 1 independent of the ROM cell 2. That state is shown in FIGS. 2A through 2D at time t1. The word line signal WL and ROM cell enabling signal RE are both transited to a `high` level. The first node A is transited to a `high` level, while the second node B is transited to a `low` level. The hybrid memory device is in a disabled state at time t2 and time t4.
However, the related art has various disadvantages. Since the cell nodes of the SRAM cell 1 are connected with the ROM cell in the hybrid memory device, when the data in the ROM cell 2 is externally required, data in the SRAM cell 1, different from the data in the ROM cell 2, is destroyed. In addition, because the SRAM and ROM cells 1, 2 have common nodes, the data is stored in the first and second NMOS transistors NE1, NE2 at different levels. Thus, a SRAM cell must be provided to a ROM cell, resulting in decreased integration.
The above description and other related art of hybrid memory are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.